1. Field of the Invention
The invention relates to the field of integrated circuit design, and in particular, to a system and method for efficiently and accurately detecting patterns in a circuit layout that are likely to generate pinch and bridge conditions during lithography.
2. Related Art
An electronic design automation (EDA) system is a computer software system used for designing integrated circuit (IC) devices. The EDA system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.) and translates (“synthesizes”) this high-level design language description into netlists of various levels of abstraction. A netlist describes the IC design and is composed of nodes (functional elements) and edges, e.g., connections between nodes. At a higher level of abstraction, a generic netlist is typically produced based on technology independent primitives.
The generic netlist can be translated into a lower level technology-specific netlist based on a technology-specific (characterized) cell library that has gate-specific models for each cell (i.e., a functional element, such as an AND gate, an inverter, or a multiplexer). The models define performance parameters for the cells; e.g., parameters related to the operational behavior of the cells, such as power consumption, delay, and noise. The netlist and cell library are typically stored in computer readable media within the EDA system and are processed and verified using many well-known techniques.
FIG. 1 shows a simplified representation of an exemplary digital ASIC design flow. At a high level, the process starts with the product idea (step E100) and is realized in an EDA software design process (step E110). When the design is finalized, it can be taped-out (event E140). After tape out, the fabrication process (step E150) and packaging and assembly processes (step E160) occur resulting, ultimately, in finished chips (result E170).
The EDA software design process (step E110) is actually composed of a number of steps E112–E130, shown in linear fashion for simplicity. In an actual ASIC design process, the particular design might have to go back through steps until certain tests are passed. Similarly, in any actual design process, these steps may occur in different orders and combinations. This description is therefore provided by way of context and general explanation rather than as a specific, or recommended, design flow for a particular ASIC.
A brief description of the components steps of the EDA software design process (step E110) will now be provided. During system design (step E112), the designers describe the functionality that they want to implement and can perform what-if planning to refine functionality, check costs, etc. Hardware-software architecture partitioning can occur at this stage. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Model Architect, Saber, System Studio, and Designware® products.
During logic design and functional verification (step E114), the VHDL or Verilog code for modules in the system is written and the design is checked for functional accuracy. More specifically, the design is checked to ensure that it produces the correct outputs. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include VCS, VERA, DesignWare®, Magellan, Formality, ESP and LEDA products.
During synthesis and design for test (step E116), the VHDL/Verilog is translated to a netlist. The netlist can be optimized for the target technology. Additionally, the design and implementation of tests to permit checking of the finished chip occurs. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Design Compiler®, Physical Compiler, Test Compiler, Power Compiler, FPGA Compiler, Tetramax, and DesignWare® products.
During design planning (step E118), an overall floorplan for the chip is constructed and analyzed for timing and top-level routing. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Jupiter and Floorplan Compiler products.
During netlist verification (step E120), the netlist is checked for compliance with timing constraints and for correspondence with the VHDL/Verilog source code. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include VCS, VERA, Formality and PrimeTime products.
During physical implementation (step E122), placement (positioning of circuit elements) and routing (connection of the same) is performed. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include the Astro product.
During analysis and extraction (step E124), the circuit function is verified at a transistor level, this in turn permits what-if refinement. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include Star RC/XT, Raphael, and Aurora products.
During layout verification (step E126), various checking functions are performed to ensure correctness for: manufacturing, electrical issues, lithographic issues, and circuitry. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include the Hercules product.
During resolution enhancement (step E128), geometric manipulations of the layout are performed to improve manufacturability of the design. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include the iN-Phase, Proteus, and AFGen products.
After resolution enhancement (step E128), another layout verification operation (step E129) is performed to ensure that the geometric manipulations performed during step E128 have not introduced any unintended problems (e.g., mask manufacturing rule violations and layout patterns that could cause lithographic defects). An exemplary EDA software product from Synopsys, Inc. that can be used at this step is the SiVL product.
Finally, during mask data preparation (step E130), the “tape-out” data for production of masks for lithographic use to produce finished chips is performed. Mask data preparation is sometimes referred to as “mask synthesis”. Exemplary EDA software products from Synopsys, Inc. that can be used at this step include the CATS(R) family of products.
Note that once mask production (and chip manufacturing) begins, any changes to the design layout become very expensive. Therefore, layout verification (i.e., steps E126 and/or E129) is a critical gateway in the overall design flow, since problems that are not identified during verification will typically not be detected until manufacturing defects in actual processed wafers are discovered. This results in both mask and wafer wastage, and hence, large cost and schedule penalties.
FIG. 2 shows a simplified view of a lithography operation in which a mask 210 that includes a mask pattern 220 is used to expose an exposure pattern 240 onto a wafer 230. Radiation emitted from an exposure source 290 partially blocked by opaque (lightly shaded) regions of mask pattern 220 and partially transmitted by transparent (unshaded) regions of mask pattern 220, thereby allowing mask pattern 220 to be projected onto wafer 230 to generate exposure pattern 240.
Note that exposure pattern 240 will generally not match mask pattern 220 due to various optical effects (e.g., diffraction) that occur during the exposure process. This distortion of exposure pattern 240 relative to mask pattern 220 is increased as the sizes of the elements in mask pattern 220 are reduced and the complexity of the mask pattern 220 is increased.
Two of the most common and most problematic defects that arise from this type of distortion are “pinch” defects and “bridge” defects. A pinch defect is an excessive narrowing of an element in an exposure pattern, such as indicated by pinch defect 241. This narrowing can undesirably affect device performance (e.g., by increasing line resistance). Meanwhile, a bridge defect is an excessive diminishment of a gap between adjacent elements, such as indicated by bridge defect 242. Pinch and bridge defects can lead to diminished or inconsistent device performance (e.g., by increasing resistance (pinch) or creating shorts (bridge)) and reduced output yield.
Thus, one of the key goals of layout verification (steps E126/E129 in FIG. 1) is to detect portions of the mask layout that are likely to generate pinch and bridge defects. Traditionally, this detection has been performed via physical verification of the layout. Physical verification involves performing a dimensional check of a layout to identify any elements or element groupings in that layout that exhibit dimensional characteristics that have been deemed problematic (i.e., likely to generate pinch/bridge defects if used in an actual lithography operation).
For example, FIG. 3A depicts a general set of layout dimensions that can be checked during physical verification. FIG. 3A shows a top view of a simplified mask layout 320 (in this case, the mask layout corresponding to mask pattern 220 in FIG. 2) that includes mask layout elements ME1, ME2, ME3, and ME4. A variety of spacings S1 through S5 between mask layout elements ME1–ME4 are depicted (for clarity, not all spacings are labeled). Note that two layout elements may exhibit a variety of spacings, depending on the shape(s) of those elements. For example, because layout element ME1 is L-shaped, layout elements ME1 and ME2 are separated by a first spacing S1 and a second spacing S2, due to the L-shape of layout element ME1.
In a conventional physical verification operation, spacings S1 through S5 would then be evaluated to identify any problematic locations. For example, the portion of layout element ME2 adjacent to the tips of layout elements ME1 and ME3 may generate a pinch defect in an exposure pattern (projected layout) produced using mask layout 320. Therefore, during physical verification, that portion of layout element ME2 may be flagged as a potentially problematic region if the values of spacings S2 and S3 are below a pinching threshold value. Meanwhile, the relatively long facing edges of layout elements ME2 and ME4 can generate bridging defects in the exposure pattern. Accordingly, during physical verification, the facing edges of layout elements ME2 and ME4 may be flagged if spacing S4 is less than a bridging threshold value. In this manner, physical verification can be used to identify potentially problematic portions of a mask layout.
Unfortunately, the verification of lithographic manufacturability in modern IC designs (layout elements having sub-100 nm dimensions) can be beyond the capabilities of conventional physical verification techniques. Two dimensionally identical element groupings in a mask layout may produce different projected images on a wafer due to process variations. Advanced resolution enhancement technologies (step E128 shown in FIG. 1) such as optical proximity correction (OPC) and assist features that enhance the printability of a layout design (i.e., the match between the mask layout and the projected layout) further reduce the applicability and effectiveness of physical verification.
Consequently, modern layout verification generally involves what is known as simulation-based verification (or lithography-based verification). In simulation-based verification, advanced models of the lithography processes for actual IC production are used to generate an expected exposure pattern for a mask layout. For example, FIG. 3B shows a simulated exposure pattern 340 that could be generated from mask layout 320 shown in FIG. 3A. Simulated exposure pattern 340 represents the pattern expected to be exposed onto a wafer by mask layout 320 using a particular lithography process (with simulated exposure pattern elements SE1 through SE4 corresponding to mask layout elements ME1 through ME4, respectively, in FIG. 3A). By evaluating simulated exposure pattern 340, pinch defects (such as in region P1) and bridge defects (such as in region B1) can be directly identified. The portions of the original mask layout (320) corresponding to the location of those (simulated) pinch and bridge defects can then be modified as appropriate to prevent the formation of such defects in production wafers.
In this manner, simulation-based verification provides a means for picking out problem areas of a mask layout. Unfortunately, performing the accurate lithographic simulation on the complex mask patterns required for modern IC designs is very computationally expensive. Therefore, simulation-based verification can add significantly to the cycle time of an EDA process. In many instances, the additional delays that are introduced can make simulation-based verification infeasible, despite the significant benefits provided in the detection of pinch and bridge defects.
Accordingly, it is desirable to provide a system and method for efficiently and accurately detecting regions susceptible to pinch and bridge defects in an IC design layout.